Title	::	Genetic Based Multi Objective Optimization for OFDMA System Analysis
Country	::	India
Authors	::	B.Sindhupriya || S.Kalaivani || S.Kanmani || Ms.P.Dharsana
Page	::	01-05

In This Paper We Consider Pre-Coder Based Peak Power Reduction For OFDMA Broadcast System Under The Constraint That Each Symbol Are Mutually Coupled With Considerable Qos. The Motivation For This Is That To Carry Out Power-Reduction And Jointly Considered With BER Reduction Schemes In Large-Scale OFDMA Systems. MATLAB Simulation And Numerical Results Show That, BER Conditions On The Channel Gains, A Novel Pre-Coded Scheme Systems Produced Optimized Performance Results With Threshold Scheme The Inherent Peak-To-Average Power Ratio (PAPR) Problem Is Mitigated. This Key Idea Is Extend To Propose Genetic Scheme Where The Objective Function Is Iteratively Performed With Improved Fitness Evaluation. Experimental Results Show That Genetic Scheme Outperforms All Other State-Of-The-Art Methods In Terms Of BER Rate With The Maximum PAPR. Here We Compare Both BET Simulation Results And CCDF Power Levels To Validate The Optimization Models Over Multi User Environments And Its Computational Complexity Reduction Is Proved Against Conventional Other Scheme.

 

Keywords: -Genetic Algorithm (GA), Peak To Average Power Ratio (PAPR), Orthogonal Frequency Division Multiple Access (OFDMA).

[1] T. L. Marzetta, "Noncooperative Cellular Wireless With Unlimited Numbers Of Base Station Antennas," IEEE Transactions On Wireless Communication, Vol. 9, No. 11, Pp. 3590-3600, Nov. 2010.
[2] Te-Lung Kung, Keshab K. Parhi, "Optimized Joint Timing Synchronization And Channel Estimation For OFDM Systems," IEEE Wireless Communication Letters, Vol. 1, No. 3, Pp. 149-152, June. 2012.
[3] C. Studer And G. Larsson, "PAR-Aware Large-Scale Multi-User MIMOOFDM Downlink," IEEE Journal On Selected Areas In
Communication, Vol. 31, No. 2, Pp. 303-313, Feb. 2013.
[4] S. K. Mohammed, E. G. Larsson, "Per-Antenna Constant Envelope Precoding For Large-Scale Multi-User MIMO Systems," IEEE Transactions On Communication, Vol. 61, No. 3, Pp. 1059-1071, Mar. 2013.
[5] Daiming Qu, Li Li, Tao Jiang. "Invertible Subset LDPC Code For PAPR Reduction In OFDM Systems With Low Complexity,"
IEEE Transactions On Wireless Communications, Vol. 13, No. 4, Pp. 2204 - 2213, Apr. 2014.

Title	::	QR Pattern Driven Hardware Obfusfication and High- Level Transformations
Country	::	india
Authors	::	Y.Nisha || S.Sangeetha || Mr.V.Kishore Kumar
Page	::	06-10

In Recent Years Piracy Over Digital System Is Emerging And Hardware Security Is Aim To Thwart, Overbuilding, And Reverse Engineering (RE) By Obfuscating And/Or Camouflaging. However, These Techniques Incur High Complexity And Power Overheads, And Structural Changes Cannot Provide Any Protection For The Gate-Level Netlist Of The Third Party Intellectual Property (IP) Core Or The Single Large Monolithic IC. In Order To Circumvent These Weaknesses, In This Work We Carried Out QR Code Pattern Driven Functional Obfusfication And Elaborately Analyzes Security Levels And Proposes A Practical Logic Obfuscation Method Over FIR DSP Digital Design With Low Overheads Which Prevent An Adversary From RE Both The Gate-Level Netlist And The Layout-Level Geometry Of IP/IC And Protect IP/IC From Piracy And Overbuilding. Experimental Evaluations Demonstrate The Low Area, Power, And Zero Performance Overhead Of The Proposed Obfuscation Technique.

Keywords: - Finite State Machine (FSM), Register Transfer Level (RTL) , Intellectual Property (IP) Etc.

[1] B. Davis, "Signal Rich Art: Enabling The Vision Of Ubiquitous Computing," Proc. SPIE 7880: Media Watermarking, Security,
And Forensics III, N. D. Memon, J. Dittmann, A. M. Alattar, And E. J. Delp III, Eds., Vol. 788002, Feb. 2011.
[2] S. Poslad, Ubiquitous Computing: Smart Devices, Environments And Interactions, John Wiley & Sons, Chichester, UK, 2009.
[3] E. Ouaviani, A. Pavan, M. Bottazzi, E. Brunclli, F. Caselli, And M. Guerrero, "A Common Image Processing Framework For 2D
Barcode Reading," In 7th Int. Conf. On Image Process. And Its Appl., Vol. 2, No. 465, Pp. 652–655, Jul. 1999.
[4] C. Zhang, J. Wang, S. Han, M. Yi And Z. Zhang, "Automatic Real-Time Barcode Localization In Complex Scenes," In IEEE Int.
Conf. On Image Processing, Pp. 497-500, 2006.
[5] H. Yang, A. C. Kot, And X. Jiang, "Accurate Localization Of Four Extreme Corners For Barcode Images Captured By Mobile
Phones," Proc. IEEE Int. Conf. On Image Processing, Pp. 3897-3900, 2010.

Title	::	Resource Efficient Multi Ported Sram Based Ternary Content Addressable Memory
Country	::	India
Authors	::	S.Parkavi || S.Bharath
Page	::	11-18

Static Random Access Memory Is Constructed From Ternary Content Addressable Memory Which Provides TCAM Functions By Following It With SRAM. However In SRAM, The Following Of TCAM Suffers From Reduced Memory Efficiency While Map In The TCAM Table. This Is Because Of Low Physical Address And Limited Capacity In SRAM. The Optimal Resource Of Memory Architecture Is Resource Efficient Of TCAM. The Address Information Or Stored In Multiple Virtual Blocks Of SRAM Which Is Presented In The TCAM Table. In Mapping A Greater Position Of TCAM It Increases The Overall Address Space In SRAM Unit. The Overall Followed TCAM Bits/SRAM In A Reduced Throughput. A 512 X 72bit Of Resource Efficient SRAM Based TCAM Consumes A Few Distributed Rams Via Implementation On Xilinx SPARTAN LX9 Field Programmable Gate Array. When Comparing To The Conventional SRAM Based TCAM It Utilizes Only 3.3% Of Memory.

 

Keywords: - Field Programmable Gate Array (FPGA), Memory Architecture, Memory Throughput, SRAM Based Ternary Content Addressable Memory, Static Random Access Memory (SRAM).

[1] S. Baeg, "Low-power ternary content-addressable memory design using a segmented match line," IEEE Trans. Circuits Syst. I, Reg.
[2] Papers, vol. 55, no. 6, pp. 1485–1494, Jul. 2008.
[3] K. Pagiamtzis and A. Sheikholeslami, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE J.
[4] Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
[5] P. Mahoney, Y. Savaria, G. Bois, and P. Plante, "Parallel hashing memories: An alternative to content addressable memories," in Proc.3rd Int. IEEE-NEWCAS Conf., Jun. 2005, pp. 223–226.

Title	::	Fpga Implementation of Rounded Based Approximate Multiplier for Efficient Performance of Digital Signal Processing
Country	::	India
Authors	::	D.Marimuthu || S.Bharath
Page	::	19-26

In Recent Technology, Multiplier Plays A Significant Role Of Arithmetic Operations In DSP Applications. A Recent Development In Processor Also Follows The Significant Design Criteria Are High Speed And Power Consumption. Many Current DSP Applications Are Targeted At Portable, Battery-Operated Systems, So That Power Dissipation Becomes One Of The Primary Designs Constrains. Since Multipliers Are Rather Complex Circuits And Typically Operate At A High System Clock Rate. In These Paper, Here Proposing Both Signed And Unsigned Multiplications In Rounded Based Approximate Multiplier. The Digital Reconfiguration Of Finite Impulse Response Architecture Is Inherently Support Multiplier Constant Multiplication (MCM) Technique............

 

Keywords - FIR Filter, MCM Technique, ROBA Multiplier, Signed Operations, Unsigned Operations.

[1] Asant Kumar Mohanty, Senior Member, IEEE, And Pramod Kumar Meher, Senior Member. "A High-Performance FIR Filter
Architecture For Fixed And Reconfigurable Application," IEEE.
[2] A. Umasankar, N.Vasudevan, N.Kirubanandasarathy, "Area Efficient And Low Power Reconfiurable FIR
[3] Filter," Ijcsns International Journal Of Computer Science And Network Security. Vol.15 No.8, August 2015.
[4] Balu, Venkatesan.K,Hardware "Efficient Reconfigurable Fir Filter," International Journal Of Engineering Research And
Development.
[5] F. Farshchi, M. S. Abrishami, And S. M. Fakhraie "New

Title	::	Design And Implementation Of Low Power Multiplier Using Reversible Logic Gates
Country	::	India
Authors	::	S.Arul Jenifer || M.Suganya
Page	::	27-31

Reversible logic is one of the important technologies for low power dissipation. Reversible logic gates aims at optimizing the delay, area and power consumption. The normal set of gates such as the NAND, AND, NOR, OR, XOR and XNOR are not reversible because number of inputs and outputs are not equal, in reversible logic gates number of inputs is equal to number of outputs. Some of the reversible logic gates are Feynman gate, Fredkin gate, Double Feynman gate, Toffoli-Gate, Peres gate and HNG gate. Power consumption is one of the major drawbacks in the multiplier...............

 

Keywords - Low power multiplier, Reversible Logic gates, Tanner EDA, CMOS, T-spice.

[1] Abu Sadat md.Sayem, masashiueda,(2010)" Optimization of reversible sequential circuits" Journal of computing, Vol. 2, No. 6, NY, USA, ISSN 2151-9617.
[2] H. B. Axelsen.(2011)What do reversible programs compute? In M. Hofmann, editor, Foundations of Software Science and
ComputationalStructures, volume 6604 of LNCS, pages 42-56.
[3] A. B_erut, A. Arakelyan, A. Petrosyan, S. Ciliberto, R. Dillenschneider, andE. Lutz.(2012). Experimental veri_cation of Landauer's principle linking informationand thermodynamics. Nature, 483(7388):187-189.
[4] S. A. Cuccaro, T. G. Draper, S. A. Kutin, and D. P. Moulton.(2005). A new quantum ripple-carry addition circuit.
[5] A. De Vos and Y. Van Rentergem.(2005). Reversible computing: from mathematicalgroup theory to electronical circuit experiment. In Computing FrontiersProceeding, pages 35-44.

Title	::	High Speed RNS MAC Unit Using Prefix Topology for Low Complexity DSP Applications
Country	::	India
Authors	::	M.Saranya || Mr.A.Vijayabrabhu
Page	::	32-36

This paper, for the first time, we present prefixes topology based accumulation units with variable latency to link equations via parallel-prefix computation using various methodologies such as such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder. This work is also permitted to design high-speed and unique MAC hardware structure using vedic multiplier, thereby making them suitable for any DSP applications. To prove the hardware efficiency of the Wallace tree multiplier unit it is compared with state-of-the-art methods like high speed vedic and shift and add based DA method. Moreover, this methodology has several attractive features such as simplicity, regularity and modularity of architecture........

 

Key words: - Prefix adder, RNS, FIR design, DSP etc.

[1] S. Ravi Chandra Kishore , K.V. Ramana Rao " Implementation Of Carry-Save Adders In Fpga"Ijeat Issn: 2249 – 8958, Volume-1, Issue-6, August 2012.
[2] Ms. V.N. Chaudhary,Prof. Dr. P.R. Deshmukh "Analysis And Implementation Of Low Power Wallace Tree Multiplier" Jikrece
Nov 10 To Oct 11 | Volume – 01 ,Issue-02.
[3] Simran Kaur And Mr. Mansul Bansar " Fpga Implementation Of Efficient Modified Booth Wallace Multiplier "Thaipur
University,Pune,June2011.
[4] J.-L. Beuchat And J.-M. Muller, "Automatic Generation Of Modular Mul-Tipliers For Fpga Applications," Ieee Transactions On
Computers, Vol. 57, No. 12, Pp. 1600–1613, December,2008.
[5] Nandi, A., Saxena, A.K., Dasgupta, S.: "Enhancing Low Temperature Analog Performance Of Underlap Finfet At Scaled Gate
Lengths‟, Ieee Trans. Electron Devices, 2014, 61, (11), Pp. 3619–3624.

Title	::	A Unitary Pre-coder for Optimizing Spectrum and PAPR Characteristics of SC-FDMA Signal
Country	::	India
Authors	::	Sriharini Sundararaju || M.Padmavathi || V.Janani || Mr.M.Dayanidhy
Page	::	37-40

Single Carrier Frequency Division Multiple Access (SC-FDMA) is a promising technique compared to Orthogonal Frequency Division Multiple Access (OFDMA) for the uplink transmission because of its low peak to average power ratio .However SC-FDMA is very sensitive to carrier frequency offset(CFO) , which affect the error rate performance of the system adversely .This paper proposes an efficient signal processing technique known as fractional fourier transform (FRFT) for the Single Carrier Frequency Division Multiplexing (SCFDM) over Selective fading channel in the presence of CFO. A clear improvement has been shown in Bit error rate (BER) by using FRFT block in place of FFT block................

 

Keywords -OFDM, Bit error rate, Fourier Transform ,Peak to average power ratio, Selective fading , SCFDMA , OFDMA , FRFT .

[1] T. L. Marzetta, "Noncooperative cellular wireless with unlimited numbers of base station antennas," IEEE Transactions on Wireless Communication, vol. 9, no. 11, pp. 3590-3600, Nov. 2010.
[2] Te-Lung Kung, Keshab K. Parhi, "Optimized joint timing synchronization and channel estimation for OFDM systems," IEEE
Wireless Communication Letters, vol. 1, no. 3, pp. 149-152, June. 2012.
[3] C. Studer and G. Larsson, "PAR-aware large-scale multi-user MIMOOFDM downlink," IEEE Journal on Selected Areas in
Communication, vol. 31, no. 2, pp. 303-313, Feb. 2013.
[4] S. K. Mohammed, E. G. Larsson, "Per-antenna constant envelope precoding for large-scale multi-user MIMO systems," IEEE Transactions on Communication, vol. 61, no. 3, pp. 1059-1071, Mar. 2013.
[5] Daiming Qu, Li Li, Tao Jiang. "Invertible subset LDPC code for PAPR reduction in OFDM systems with low complexity," IEEE
Transactions on Wireless Communications, vol. 13, no. 4, pp. 2204 - 2213, Apr. 2014.

Title	::	High radix booth MAC unit using prefix topology for low complexity DSP applications
Country	::	India
Authors	::	k.Seetha lakshmi || V.Janakiraman
Page	::	41-44

This paper, for the first time, we present prefixes topology based accumulation units with variable latency to link equations via parallel-prefix computation using various methodologies such as such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder. This work is also permitted to design high-speed and unique MAC hardware structure using vedic multiplier, thereby making them suitable for any DSP applications. To prove the hardware efficiency of the Wallace tree multiplier unit it is compared with state-of-the-art methods like high speed vedic and shift and add based DA method. Moreover, this methodology has several attractive features such as simplicity, regularity and modularity of architecture..............

 

Keywords- Prefix adder, MAC, FIR design, DSP etc.

[1] S. Ravi Chandra Kishore , K.V. Ramana Rao " Implementation of carry-save adders in FPGA"IJEAT ISSN: 2249 – 8958, Volume- 1, Issue-6, August 2012. [2] Ms. V.N. Chaudhary,Prof. Dr. P.R. Deshmukh "Analysis And Implementation Of Low Power Wallace Tree Multiplier" Jikrece Nov 10 To Oct 11 | Volume – 01 ,Issue-02.
[2] Simran Kaur and Mr. Mansul bansar " FPGA IMPLEMENTATION OF EFFICIENT MODIFIED BOOTH WALLACE
MULTIPLIER "Thaipur University,Pune,June2011.
[3] J.-L. Beuchat and J.-M. Muller, "Automatic generation of modular mul-tipliers for fpga applications," IEEE Transactions on
Computers, vol. 57, no. 12, pp. 1600–1613, December,2008.
[4] Nandi, A., Saxena, A.K., Dasgupta, S.: "Enhancing low temperature analog performance of underlap FinFET at scaled gate
lengths‟, IEEE Trans. Electron Devices, 2014, 61, (11), pp. 3619–3624 .
[5] Nandi, A., Saxena, A.K., Dasgupta, S.: "Analytical modeling of double gate MOSFET considering source/drain lateral Gaussian doping profile‟, IEEE Trans. Electron Devices, 2013, 60, (11), pp. 3705–3709.

Title	::	Design of Stochastic ALU Architecture and Analysis of Digital Computation in Dynamical Systems
Country	::	India
Authors	::	R.Rajeshwari || S.Bharath
Page	::	45-54

In recent technologies, the floating point units will have high throughput in the arithmetic calculations, which have greater throughput in less time, and make easier to meet real time requirements. This can save power and extended battery life. These floating point units are followed by stochastic logic computation approach. Stochastic approach (SC) shown that the results about efficiency of the area in the low power system during the implementations of the hardware. The recent generation based applications has demand in high computational power with a minimal energy. SC is a computation format of digital system. This is followed by random bit streams for complex computations tasks, where smaller hardware is compared with conventional radix approaches..............

 

Keywords - Floating point numbers, random bit streams, stochastic numbers, and stochastic ALU design.

[1] Alaghi, C. Li, and J. P. Hayes, "Stochastic circuits for real-time image-processing applications," in Proc. Design Autom. Conf, 2013.
[2] Alaghi and J. P. Hayes, "Survey of stochastic computing," ACM Trans, Embedded Comput, Syst, vol. 12, no. 2s, 2013, Art. no. 92.

[3] R. Gaines, "Stochastic computing systems," in Advances in Information Systems Science, vol. 2, J. T. Tou, Ed. New York, NY, USA: Plenum, 1969, ch. 2, pp. 37–172.
[4] D. Brown and H. C. Card, "Stochastic neural computation I: Computational elements," IEEE Tran, Comput, vol. 50, no. 9, pp. 891– 905, Sep. 2001.
[5] J. von Neumann, "Probabilistic logics and synthesis of reliable organ-isms from unreliable components," in Automata Studies. Princeton, NJ, USA: Princeton Univ. Press, 1956, pp. 43–98.

Title	::	Obfuscation of Integrated Circits Using High Level Transformation
Country	::	India
Authors	::	N.Subasri || T.Idhayarani || N.Saranraj
Page	::	55-59

For Any Semiconductor Manufacturing Requires Greater Capital Investments, The Use Of Contract Foundries Has Grown Dramatically, Increasing Exposure To Theft And Unauthorized Excess Production. Many Recent Activities Proved That Ic Piracy Has Now Become A Major Challenge For The Electronics And Defense Industries. In This Paper We Presents A Novel Approach To Design Obfuscated Circuits For Digital Signal Processing (Dsp) Applications Using High-Level Transformations, A Key-Based Obfuscating Finite-State Machine (Fsm), And A Reconfiguration. The Goal Is To Design Dsp Circuits That Are Harder To Reverse Engineer. With Several Modes Of Operations For Obfuscation Where The Outputs Are Meaningful From A Signal Processing Point Of View, But Are Functionally Incorrect For Better Confusion............ 

 

Keywords -Digital Signal Processing (Dsp), Functional Obfuscation, Hardware Security, High-Level Transformations, Intellectual Property (Ip) Protection, Obfuscation, Reconfigurable Design, Structural Obfuscation.

[1] R. S. Chakraborty And S. Bhunia, "Rtl Hardware Ip Protection Using Key-Based Control And Data flow Obfuscation," In Proc.
23rd Int. Conf. Vlsi Design, Jan. 2010, Pp. 405–410.
[2] R. S. Chakraborty And S. Bhunia, "Harpoon: An Obfuscationbasedsoc Design Methodology For Hardware Protection," Ieee Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 28, No. 10, Pp. 1493–1502, Oct. 2009.
[3] R. S. Chakraborty And S. Bhunia, "Hardware Protection And Authentication Through Netlist Level Obfuscation," In Proc. Int.
Conf. Comput.-Aided Design, Nov. 2008, Pp. 674–677
[4] W. P. Griffin, A. Raghunathan, And K. Roy, "Clip: Circuit Level Ic Protection Through Direct Injection Of Process Variations,"
Ieee Trans. Very Large Scale Integr. (Vlsi) Syst., Vol. 20, No. 5, Pp. 791–803, May 2012.
[5] F. Koushanfar And Y. Alkabani, "Provably Secure Obfuscation Of Diverse Watermarks For Sequential Circuits," In Proc. Int.
Symp.Hardw.-Oriented Security Trust, Jun. 2010, Pp. 42–47.

Title	::	Hybrid Recoding Driven Approximated Partial Product Reduction Multiplier for DIP Applications
Country	::	India
Authors	::	M.Induja || C.Neha || H.Mahashree || Ms.G.Anuvidhya
Page	::	60-64

In This Paper, We Analyze The Tradeoff Accuracy And Energy Conservation Of Fixed Width Multiplier In DIP Applications. In Most Cases Fixed Point Arithmetic Is Used To Keep The Dynamic Ranges Within The Certain Limit Based Accuracy Trade Off Over Resource Constraints Our Proposed Approximated Multiplier Use Consecutive 4:2 Compressor Units Which Applies On Partial Products Accumulated Based On Dadda Multipliers That Includes The Leading Ones From Two Operands To An M×M Multiplier. In Most Cases Direct Truncation Approach Identifies Only The MSB Part Leads Error Propagation. An Exact Approximation Followed By Tree Based PP Reduction Gives Considerable Complexity Reduction And Also Consumes Much Less Energy And Area Than Direction Truncation Approaches...............

 

Keywords - 4:2 Compressors, Accuracy, Very Large Scale Integration (VLSI), Digital image processing (DIP).

[1] S. Yu and E. E. S. ,Jr., "DCT implementation with distributed arithmetic"IEEE Trans. Comput., vol. 50, no. 9, pp. 985–991, Sep. 2001.
[2] P. K. Meher, "Unified systolic-like architecture for DCT and DST using distributed arithmetic," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2656–2663, Dec. 2006.
[3] L. D. Van and C. C. Yang, "Generalized low-error area-efficient fixedwidth multipliers," IEEE Trans. Circuits Syst. I, vol. 52, no. 8, pp. 1608– 1619, Aug. 2005.
[4] C. H. Chang and R. K. Satzoda, "A low error and high performance multiplexer-based truncated multiplier," IEEE Trans. VLSI
Syst., vol. 18, no. 12, pp. 1767–1771, Dec. 2010.
[5] C. Lu, S. P. A.D. Booth, "A signed binary multiplication technique," Quarterly J. Mechan. Appl. Math., vol IV. Part 2, 1951.

Title	::	Cooperative Mimo Mac Using Type2 Fuzzy Logic for Wireless Sensor Network
Country	::	India
Authors	::	A.Anusuya || R.Suganya || M.suganya
Page	::	65-68

Energy Efficiency And Enhancing The Lifetime Is Very Important Design Requirements In Wireless Sensor Network (Wsns).To Improve The Network Lifetime And To Reduce The Energy Consumption Using Clustering Scheme.Cooperative Multiple Input And Multiple Output Can Be Applied And To Hence Significantly Improve The Communication Performance.An Inefficient Medium Access Control Protocolis Incorporated To Diminish The Performance Gain Of MIMO.Hence This Paper Proposes Space Time Block Codes Using Cooperative MIMO MAC Transmission. An Idea Of Type2 Fuzzy Logic Is Used For Cluster Head(CH) And Cooperative Node Selection.Cluster Head Is Selected Based On Remaining Power,Distance To Base Station And Concentration...............

 

Keywords - Cooperative Mimo,Energy Efficiency,MAC Protocol,STBC,Wireless Sensor Network(WSN),T2FL.

[1] KazemSohraby, Daniel Minoli and TaiebZnati, "Wireless Sensor Networks Technology, Protocols and Applications", John Wiley and Sons, New Jersey, 2007.
[2] Ivan Stojmenovic, "Hand Book of Sensor Network Algorithms and Architectures", John Wiley and Sons, New Jersey, 2005.
[3] Mohammad Ilyas and ImadMahgoub, "Hand Book of Sensor Networks: Compact Wireless and Wired Sensing Systems", CRC Press, Washington, 2005.
[4] Rajeev Shorey, A. Anandha, MunChoon Chan and Wei Tsang Ooi, "Mobile, Wireless and Sensor Networks Technology,
Applications and Future Directions", John Wiley and Sons, New Jersey, 2006.
[5] W. R. Heinzelman, A. Chandrakasan, and H. Balakrishnan, "Energy efficient communication protocol for wireless microsensor networks," in Proceedings of 33rd Hawaii International Conference System Sciences, Washington, pp. 1–10, Jan. 2000.